The linear ramp generating and control circuit of the present invention finds particular applicability in a measurement apparatus for measuring time intervals between signal events, wherein each measured interval comprises the summation of a coarse clock count and fine or calibrated vernier counts of the measured fractional clock periods after each START and STOP event. Such a time measurement system is disclosed in U.S. Pat. No. 4,908,784 to Box, the entirety of which is herein incorporated by reference. More specifically, the linear ramp circuit of the present invention is an improvement of the linear ramp circuit of the Box '784 device as disclosed in FIGS. 9e-f and accompanying specification. As such, the present invention concerns that portion of the total time measurement apparatus necessary to generate both a rough clock count (course count) and an uncalibrated vernier count (fine count) when provided with START and STOP signals.
As discussed in the Box '784 patent, measurement of calibrated vernier counts of the clock periods or fractional beginning and end times of any event is effectuated with a voltage address developed by associated start and stop ramp capacitive circuitry and passed to an analog to digital converter which is used to access the stored corresponding time value from a calibrated fine count memory. Recharging of the hold capacitor in the Box '784 device was effectuated through a diode clamp network to restore the baseline voltage to the hold capacitor during the recovery mode of operation. Limitations of the diode clamp circuit include relatively poor consistency and lack of repeatability between successive data samples, relatively long time constants of the hold capacitor voltage recovery (requiring increased time interval between data samples to ensure stable voltage levels), and poor thermal dependence (thermal drift).